By Himanshu Bhatnagar
The emphasis of this booklet is on real-time program of Synopsys instruments, used to strive against numerous difficulties noticeable at VDSM geometries. Readers might be uncovered to a good layout method for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to format, actual synthesis, and static timing research. At every one step, difficulties similar to every part of the layout circulate are pointed out, with ideas and work-around defined intimately. moreover, an important matters similar to structure, including clock tree synthesis and back-end integration (links to format) also are mentioned at size. moreover, the publication comprises in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding kinds, specific in the direction of optimum synthesis resolution.
aim audiences for this e-book are training ASIC layout engineers and masters point scholars venture complex VLSI classes on ASIC chip layout and DFT techniques.
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Additional info for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime®
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime® by Himanshu Bhatnagar